A Review on Important Issues in GCN Accelerator Design
Siyuan Miao · Advances in Social Science, Education and Humanities Research/Advances in social science, education and humanities research · 2022
Graph convolutional neural networks (GCNs) emerge as an efficient method to process real-world graph data and have been proved powerful in various areas like link prediction and crack detection.While the graphs in GCNs have dynamic and irregular inherent patterns, traditional hardware architectures have poor performance on GCN models and accelerators are needed.This review discusses four bottlenecks for traditional hardware which are also important issues in GCN accelerator designs.The irregular patterns of the input matrix harm the utilization of processing elements (PEs), especially for systolic array-based architectures, which can be alleviated by adopting flexible execution patterns.Then there is a problem of high adjacent matrix sparsity which decreases performance.Usual solutions include using flexible loading patterns and preprocessing adjacent matrix to reduce sparsity.The imbalanced workload in the aggregation stage makes PE utilization drop to as low as 18.3%, increasing processing latency.Therefore, a specially designed hardware architecture that enables the exchange of workloads may be efficient.Last, this review discusses the data reuse problem, which is crucial for saving memory resources.Inner product, outer product and some useful techniques are mentioned.