A Side-Channel Hardware Trojan in 65nm CMOS with $2\mu\mathrm{W}$ precision and Multi-bit Leakage Capability
Tiago Perez, Samuel Pagliarini · 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) · 2022
In this work, a novel architecture for a side-channel trojan (SCT) capable of leaking multiple bits per power signature reading is proposed. This trojan is inserted utilizing a novel framework featuring an Engineering Change Order (ECO) flow. For assessing our methodology, a testchip comprising of two versions of the AES and two of the Present (PST) crypto cores is manufactured in 65nm commercial technology. Our results from the hardware validation demonstrated that keys are successfully leaked by creating microwatt-sized shifts in the power consumption.