Formal verification - is it real enough?
Yaron Wolfsthal, R.M. Gott · 2005
While formal verification (FV) of logic designs has been described in an industrial context, it has not yet become a mainstream methodology. The purpose of this report is to summarize a body of experience in the application of industrial-scale FV. FV is a realistic means to successfully address the growing complexities of contemporary design. Introducing FV into the design flow is a strategic decision that requires investment in engineering resources (training and methodology adjustment) as well as support and commitment from management. When appropriately applied, FV is a powerful verification vehicle which contributes to increasing design quality and shortening time to market, with a notable return on the investment in engineering resources.