Accelerating Performance of a Real-time 2D Delay-Sum Beamformer on General Purpose Processors
Prakash Narayanan M, Vijay Gopal G, Raghvan Rajesh · 2021
Present day sonars uses hundreds of sensors to make big arrays. These sensors are often digitized separately and the beamformer is realized in digital data. Current processor technologies support enough computations. The processors can be effectively utilized only if the memory and cache can be managed well. This is illustrated with a typical Intel processor in which the control over memory and cache is least for the user. To get the best performance of the machine, user need to know the architectural details of the processor, and look for opportunities to get improvement in performance. This paper analyses a time domain beamformer and the cache related issues are studied. We evaluate the use of techniques specific to processor architecture as well as some general signal processing technique to achieve high-performance digital signal processing on general-purpose Intel processors. A naive implementation using dot product functions of the processor leads to a CPU bound solution in which the memory is not utilized. With increase in memory blocks sizes the utilization increases. However, after carefully tuning for a better utilization of CPU resources using Fused Multiply Add (FMA) operations, the utilization increases nearly 25 folds. This leads to a case of memory bound operation as the memory manager is unable to feed the computational resources with data at the rate it is processing. The detailed results will be presented towards the end of the paper.