A Single Precision Floating Point Multiplier for Machine Learning Hardware Acceleration
Hao Li · 2021 IEEE Conference on Telecommunications, Optics and Computer Science (TOCS) · 2021
A single precision floating-point multiplier based on FPGA is designed. The booth-2 algorithm is used for the encoding operation, and the Wallace tree structure is used to complete the accumulation of partial products. A 32-bit single precision floating-point multiplier based on IEEE754 standard is designed. The multiplier can be used as the basic structure of hardware multiplier to accelerate Convolutional Neural Networks algorithm.