A Promising PE-PUF Structure Based on High Precision Delay Measurement
Ming Yang Sun, Min Zhu, Bohan Yang, Leibo Liu · 2021 IEEE 6th International Conference on Signal and Image Processing (ICSIP) · 2021
Physical Unclonable Function (PUF) has proved to be a promising primitive for hardware security, which extracts entropy from the IC manufacturing process variations. The delay-based PUFs such as Ring Oscillator PUF（RO PUF） and Arbiter PUF have received a great deal of attention. In this paper, we present a promising delay-based PUF architecture, called Processing Element-PUF (PE-PUF) that exploits the circuit delay variations existing in the processing elements. We apply a system clock with incremental frequency to a pair of PE modules, and one output bit of PE-PUF is determined by the information which PE module of the pair fails first. A prototype implementation of PE-PUF is validated on Digilent Nexys A7 FPGAs. Compared with conventional delay-based PUFs, the proposed PE-PUF can mitigate the counter failure problem. Moreover, the PE-PUF utilizes the intrinsic delay of existing processing elements of reconfigurable processor, which leads to a compact implementation. Similar methodology could be applied to other system where a collection of combinatorial circuits could be driven by a tunable clock.