Introduction to Verilog HDL
Suman Lata Tripathi, Sobhit Saxena, Sanjeet Kumar Sinha, Govind Singh Patel · 2021
Verilog is a type of hardware description language (HDL). This language is used to describe the hardware for the purpose of simulation, synthesis, and implementation. This chapter describes the basics of design and analysis of HDLs. The behavior of Verilog is similar to behavioral and structural language. Its internal module can be divided into four levels of abstraction. The chapter also describes the details of each module. The lexical tokens, used in Verilog, are similar to programing in C. It is case-sensitive language and, in this language, all keywords are in lowercase. The chapter provides information on a few conventions. The testbench concept is also called a stimulus. The main module is used to generate RTL of the design. The main module may be changed as per each level of abstraction, whereas test is the same for all types of modeling.