Network-on-Chips for Future 3D Stacked Dies (Invited)
Tiago Mück · 2021
Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. Current infrastructure SoCs, such as Arm Neoverse based platforms, provide a large number of cores (e.g. 64-128 cores) integrated using one or more large mesh-based topologies (e.g. 8x8 meshes). Future SoCs are expected to grow even larger both in terms of number of cores and mesh size (10x10 and beyond). These large meshes, however, introduce longer memory access and core-core communication latency, as well as a tendency for congestion hotspots in heavy traffic scenarios. Meanwhile, advances in 3D integration technologies create a new design space to explore 3D interconnect solutions that allow us to address these problems. In this talk we will discuss new 3D NoC topologies for 3D stacked dies as well as flat 2D topologies with express links (XL). XLs (based on the concepts Ruche Networks can leverage the wiring capabilities on additional layers in a 3D SoC to create long-range physical channels between non-adjacent tiles in the same dimension in the mesh. XLs can increase the available bandwidth and provide latencies comparable to smaller mesh topologies.