FPGA Implementation of Interleaved Modular Multiplier with Improved Area-time Efficiency
Radu‐Mihai Coliban · 2021 11th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS) · 2021
Modular multiplication is the fundamental operation in Elliptic Curve Cryptography (ECC) and a multitude of hardware implementations have been developed so far. In this paper, a series of modifications to a high performance radix-2 interleaved modular multiplication architecture are proposed. The design was implemented on a Virtex-7 FPGA for five prime fields recommended for ECC by the National Institute of Standards and Technology (NIST), showing a significant improvement in area-time efficiency in comparison to the original architecture.