Selective Fault-Masking for Improving Yield and Performance of On-Chip Networks
Biswajit R. Bhowmik, Jatindra Kumar Deka, Santosh Biswas · 2021 IEEE International Conference on Systems, Man, and Cybernetics (SMC) · 2021
Nowadays, the reliability in network-on-chip (NoC) has become a crucial issue that leads to network performance degradation. Built-in-self-test (BIST) is one of the primary test schemes often used to achieve high reliability. The scheme allows a frequent test of and recovery from faults experienced on an NoC’s fundamental component, e.g., communication channels. This paper presents a BIST approach that detects open and short faults in communication media to demonstrate the fault-masking phenomenon. The phenomenon as the self-repairing mode of the communication media improves the yield and performance of the NoCs. Rigorous simulations are made on an 8×8 mesh NoC with faulty and repaired channels. Results reveal that allowing faults in communication tracks degrades the network performance up to 30% while the self-repairing mode improves nearly 75%.