Fail-Safe Neural Network Inference Accelerator
Mihir Mody, Prithvi Shankar, Veeramanikandan Raju, Sriramakrishnan Govindarajan · 2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) · 2021
Deep learning techniques like Convolution Neural Networks (CNN) are nowadays popular for performing many artificial intelligence tasks (e.g. object detection, semantic segmentation) across market segments. Automotive and Industrial market segments especially, are finding a lot of traction in using these techniques to solve several problems. These markets have higher functional safety goals due to potential impact of failure resulting in severe consequences including loss of life. The traditional approach to achieve higher safety goal for hardware is full redundancy, which has inherent disadvantage of doubling cost and power of given solution. This paper presents novel and area efficient hardware architecture using matrix checksum properties and duplication of nonlinear operations to enable higher safety goal for NN computation. The paper also proposes multiple architecture variations which allow trade-offs ranging from full performance throughput, low latency error detection to lowest area solution. The proposed solution is designed and simulated in Python HDL. The proposed solution can be realized with 5% additional silicon area as matrix computation is nearly majority part of NN computation. The simulation shows benefits of solution i.e. full performance throughput, while single errors in input matrix and matrix multiplications getting detected, meeting functional safety goals.