Implement 32-bit RISC-V Architecture Processor using Verilog HDL
Jin-Yang Lai, Chiung-An Chen, Shih‐Lun Chen, Chun-Yu Su · 2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) · 2021
RISC-V is a very novel ISA(instruction-set architecture) recently launched features such as low power consumption, low cost, and scalability. In the future, IoT(Internet of Things) devices will be developed in a large amount, and the characteristics of RISC-V are exactly what IoT devices need. Therefore, in this paper, using verilog to design a RISC-V processor that supports the RV32I instruction set, and use Modelsim to verify whether it conforms to the instruction set architecture definition, and confirm the usability of this processor.