Implementation of 32-bit RISC Microprocessor on ZedBoard
Astha Maheshwari, Dhanush S Hulgur, Pratheek Sharath, S Jamuna · 2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) · 2021
Computer engineering and VLSI design industries are greatly burdened with the trade-offs between the cost and performance of components in the implementation domain. Reduced Instruction Set Computer (RISC) architecture relies its focus mainly on scaling down the complexity and the number of instructions in the microprocessor. The most important feature of RISC is that it supports load/store architecture. With this feature, an optimized 32-bit microprocessor has been designed with Verilog, simulated and synthesized in Vivado and implemented on Xilinx ZedBoard FPGA. The designed processor uses 32-bit instruction format with an instruction set of 32 instructions where each instruction executes in 4 clock cycles. The design includes all the primary subsystems such as ALU, Shifter and Rotator, Multiplier etc., and a Control Logic to control the data flow. Memories such as Instruction Memory (256x32bit) and Data Memory (256x64bit) are also designed. The whole microprocessor is built in a modular fashion with the integration of these subsystems and memories and is highly optimized in terms of timing, utilization and power.