Energy Efficient Adiabatic Logic Against Power Analysis Attacks for IOT Applications
Sravanthi Parepalli, Ramesh Kumar Aytha, Sagar Reddy Vumanthala · 2021
This paper presents an efficient way of protecting the cryptographic circuits against the power analysis attacks(P AA) using positive feedback adiabatic logic. The conventional circuit is improvised by adding a dummy transistor circuit which provides a symmetric optimized path for the current flow in the circuit. The EE-CPO-SPFAL logic is been proposed, designed and simulation results are provided by using Hspice-A 2008.03. From the simulation reports of the proposed logic, the current fluctuations are reduced by 41 % and also the energy consumption fluctuations are being reduced by 76% compared to the previous logic CPO-SPGAL. Thereby ensuring more protection against the power analysis attacks compared to the existing logic theories.