Performance Analysis of Parallel FIR Digital Filter Based on Even Symmetric Fast FIR Algorithm using Different Adders
S. Narendran, B. T. Geetha · 2021 5th International Conference on Electronics, Communication and Aerospace Technology (ICECA) · 2021
The ultimate goal of the research work is to analyze the performance of FIR filter designed based on FFA algorithm. The proposed structure aims at area-optimized adders which are designed for symmetric coefficient that reduces hardware cost in the design with a constrain that the filter tap is of even order. Area analysis of silicon chip is performed using different adders like Ripple Carry Adder (RCA), Carry Look-Ahead Adder (CLA) and Conditional Sum Adder (COS). Performance analysis report for a 3 parallel 96-tap filter is considered based on the above adder, where the RCA requires less area utilization compared to other three adders. The symmetric convolution-based RCA Fast FIR Algorithm (FFA) structure requires only 896 slices whereas COS requires 1024 slices and CLA requires 960 slices. For higher-order, FIR filter structure of 1024 or higher taps, the savings in the area utilization for RCA based FFA is approximately 10% and 15% compared to CLA and COS basedFFA respectively because COS requires more hardware building blocks. The RCA based FFA increases the latency by approximately 9% and 7% compared to CLA and COS based FFA respectively, and there will be a trade-off.