Analysis and Low-power Hardware Implementation of a Noise Reduction Algorithm
Ang Wang, Lina Yu, Yuyan Lan, Weixin Zhou, Wan’ang Xiao · 2021
In order to reduce noise and power consumption of audio electronic products, audio noise reduction and its low- power hardware implementation is studied. Considering the noise reduction effect and the amount of calculation, Log-MMSE algorithm and statistical-model-based Voice Activity Detection (VAD) noise estimator is selected in this paper. And the amount of calculation is optimized at the algorithm level. The ability of tracking non-stable noise is simulated and studied, and a possible noise reduction failure in hardware applications is prevented. In the hardware design, the existing memory is reused to save an extra memory. Two special operations are combined with one operation, and approximate calculations are implemented according to the characteristics of the combined operation. The design of this paper has passed the functional verification on FPGA and taped out with a digital hearing aids chip under the SMIC 0.13μm Mixed Signal Process. The area and the post-simulation power consumption under the tt process corner are 0.206mm2and 15.3μW respectively, which meet the requirements of low-power audio chip.