An FPGA-based Power-saving Particle Filter Using Dynamic Reconfiguration
Yuta Imamura, Shota Fukui, Taito Manabe, Yuichiro Shibata · 2021
In this paper, we discuss an FPGA implementation of a power-saving particle filter which can dynamically change the number of particles by making the best use of dynamic reconfigurability of the FPGA. In an object tracking process with a particle filter, it is considered that the tracking can be performed even with a small number of particles when the target object is easy to be tracked. Focusing on this point, we propose to reduce the power consumption of particle filter hardware by changing the number of particles at the circuit level with dynamic reconfiguration depending on the easiness of tracking. As a result of evaluation, it is found that the power consumption can be reduced by about 30% when the number of particles is adjusted using the effective sample size (ESS) as a metric, compared with the case of the fixed number of particles, if the overhead of dynamic reconfiguration is not included.