A Multi-Polynomial CRC Circuit for 5G Standard Using Parallel Pipelining Architecture
Jiahao Pan, Shida Zhong, Peichang Zhang, Tao Yuan · 2021 Cross Strait Radio Science and Wireless Technology Conference (CSRSWTC) · 2021
This paper proposed a novel parallel pipelining multi-polynomial CRC circuit for high speed data calculation in 5G wireless communication while remaining efficient hardware resource usage, which can dynamically switch calculation between multiple CRC polynomials. The proposed CRC circuit is designed using VHDL and synthesis results are valided on Altera (Intel) Stratix IV FPGA (EP4SGX230KF40C2).