Optimization of Logical Resources in Reconfigurable Computing
S Jamuna · Applied Soft Computing · 2021
A computing system which can be reconfigured depending on the functionality requirement is called as a reconfigurable computing system. Such kind of a computing system can be easily implemented using reconfigurable device, i.e., a reconfigurable field programmable gate arrays (FPGAs). Computing systems are designed using reconfigurable devices so that they can adapt and evolve in response to the changing application environment while executing the assigned task. At present FPGAs are used in almost all applications like space missions, communication systems, automotive and industrial applications etc. In any digital system design, it is very important to optimize parameters such as processing time, power consumption, memory requirements and hardware resources, etc. In FPGAs number of logic resources utilized will depend upon the complexity of the application design. Since the availability of logic resources is fixed for any FPGA, there is an option for the designer to utilize efficiently. Run time re-configurability feature available in recent FPGAs helps the designer to implement multiple functionalities with time multiplexed hardware. Partial reconfiguration facilitates run-time re-configurability. SoC functional blocks mapped on high-end FPGAs can be partially reconfigured without affecting system’s 70normal functionality. PR design methodology enables new types of FPGA designs that provide efficiencies unattainable with conventional design techniques [1]. In this chapter an attempt is made to explain how the number of logical resources utilization can be reduced through partial reconfiguration. Three case study applications are illustrated in support of this. Design and implementation of ALU block, the modulation functional blocks and encryption algorithms on FPGA are explained. Design is been done using XILINX Vivado software and implemented on ZED board.