A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching
Pingcheng Dong, Zhuoao Li, Zhuoyu Chen, Ruoheng Yao, Huanshihong Deng, Wenyue Zhang, Yangyi Zhang, Lei Chen, Chao Wang, Fengwei An · 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) · 2021
Binocular stereo matching is an essential topic in computer vision. However, the high complexity and massive computation restrict its applicability in real-time. To cache large amounts of data, the primary method [1] involved an external DRAM and reached 133MHz, but power consumption is as high as 2.313W on the Virtex-5 FPGA platform. In addition, a fully parallel and pipelined architecture based on dependency relaxation [2] attained a processing speed of 81 fps performed on Virtex-7, whose error rate is 10.5% based on the KITTI 2015 dataset with 64 disparity range. Another two-cycle time-sharing pipelined architecture [3] reaches 200MHz with a 128 disparity range on VCU-118. A compact hardware architecture is still challenging research [4 $\sim$ 6].