Improving the Operating Efficiency of a Multibit Binary Parallel-Prefix Adder
Alexey N. Yakunin, Aung Myo San, Han Myo Htun · Russian Microelectronics · 2021
Abstract For the fast addition of two multibit binary numbers, parallel-prefix adders (PPAs) are currently considered effective. Several PPAs are known with different time and hardware characteristics, and in particular, the Kogge–Stone adder is faster than other PPAs. However, this adder has a large number of logical elements and, therefore, occupies a large area, which leads to an increase in its price. This paper analyzes the Kogge–Stone adder. To reduce its hardware and time costs, a modified PPA is developed. Adders are compared in terms of the occupied area and the maximum delay of an operation. A results’ verification scheme is implemented to confirm the reliability of the modified adder’s operation. This circuit is simulated in the CAD Altera Quartus-II environment. As a result, it is found that when performing operations with 32- and 64-bit operands, the developed adder reduces the occupied area by 11 and 16.5%, respectively, and the maximum delay by 7%, compared to a Kogge–Stone adder.