Embedded Compute Matrix Processing and FFTs using Floating Point FPGAs
Michael Parker · 2021
FPGAs are able to support signal processing usually reserved for CPUs or GPUs. Complex algorithms, with extreme parallelism, can be implemented in FPGAs using single precision floating point. The FPGA provides very low and deterministic latency and can operate in challenging embedded processing environments. This paper will detail implementation and performance of two representative algorithms, the QR Decomposition and FFT, as well describe the methods used to achieve high degrees of parallel processing, computed using single precision floating point numerical representation.