Fault Tolerant Reversible T Latch with Enhanced Testability at Nano-Scale for Application of Ripple Counters
Pankaj Singh, Rupali Singh · Russian Microelectronics · 2021
Abstract Reversible logic is an attracting approach to design the circuits with low power consumption. The cusp of reversible logic and Quantum dot cellular automata (QCA) ease out the design of low power, high speed and nano size circuits. This paper targets the layout design of fault tolerant, reversible, QCA based T latch which can potentially contribute to the design of large sequential circuits. The proposed reversible T latch is designed using a novel QCA layout of Peres gate. The proposed QCA layout of Peres gate has improved performance over the earlier QCA based reversible gates. Its cost function is improved by 50.6% and power dissipation is reduced by 46.62%. Also, the QCA layout of proposed T latch achieved an improvement of 68.77% in cost function as compared to earlier cost efficient design of reversible T latch. Most importantly, vigorous testing of the proposed reversible T latch was carried out against various cell defects. Furthermore, the testable reversible T latch was used as a module to design ripple counter circuits. The QCA based design of ripple counter was novel and not much addressed in the literature. Hence, the design of optimized, fault tolerant QCA layout of reversible T latch is a noteworthy step towards future design of digital circuits.