B-SYS: A 470-Processor Programmable Systolic Array.
Richard Hughey, Daniel Lopresti · 1991
This paper presents an architecture for programmable systolic arrays that provides simple and efficient systolic communication. The Brown Systolic Array is a linear implementation of this Systolic Shared Register architecture; a working 470-processor prototype system performs 108 MOPS. A 32-chip, 1504-processor implementation could provide 5 GOPS of systolic co-processing power on a single board. Keywords: systolic array, parallel processing, VLSI, SIMD, sequence comparison. Introduction The systolic array is perhaps the most significant architectural development inspired by the revolution in VLSI fabrication technology. By pumping data through a regular network of hundreds or thousands of simple processing elements, computationally intensive problems can be solved many times faster on systolic arrays than on traditional machines. Since the introduction of the systolic paradigm, systolic co-processors have been proposed to solve a wide variety of problems. However, new VLSI single-pu...