Multiprocessor memory contention
Jr. C. E. Knadler · 1989
Caches are frequently incorporated in processor architectures to increase the effective memory speed and to reduce memory contention. However, task switches and the coherency problems of large n-way, mainframe-class multiprocessors lessen the effectiveness of cache architectures for general purpose applications. A proposed alternative approach is to increase the effective memory bandwidth and decrease memory access delays through instruction prefetch, operand buffering, highly interleave memory, and multiple-word width processor-memory data paths. This approach was evaluated by comparing cache and noncache system performance, using discrete event simulation. Since the performance of a multiprocessor architecture is a function of its operating environment as well as its design, the system workload was defined. General purpose applications, running under multitasking operating systems, were characterized with respect to addressing patterns, paging rates, and frequency of input/output operations. This characterization was incorporated into the simulations of the cache and noncache architectures. The proposed noncache architecture was found to have performance comparable to that of the cache architectures and obviated the need to solve the cache coherency problem. The sensitivity of system performance to workload characteristics was evaluated and the performance of the proposed architecture will improve relative to the cache systems, if the current trends of decreasing memory cost and increasing memory speed continue and the ratio of main memory speed to cache speed increases.