Plenary lecture VI: heterogeneous reconfigurable chip multiprocessors for embedded systems
Sotirios G. Ziavras · Annual Conference on Computers · 2008
Chip multiprocessing has recently become a common practice in processor design. With ever increasing concerns for energy consumption, performance-energy trade-offs are often necessary, especially in the design of real-time embedded systems. Multiprocessor heterogeneity is a successful design paradigm for high performance and energy conservation with embedded systems. Performance and energy analyses will be presented for an in-house developed FPGA - based mixed-mode heterogeneous chip multiprocessor, where the SIMD (Single-Instruction, Multiple-Data) and MIMD (Multiple-Instruction, Multiple-Data) parallel computing modes can be realized simultaneously or distinctly. The presented performance-energy trade-off techniques are based on the observation that SIMD and MIMD tasks involve substantially different amounts of computation and communication with different execution time and energy behaviors. Experimental results on Xilinx FPGAs demonstrate the effectiveness of the proposed approach. To conserve space and power as well as to incorporate dynamic adaptability in embedded systems, it is important to utilize hardware components as best as possible. The hardware customization of application kernels reduces the execution time and potentially the power consumption. Reconfiguring the same hardware to facilitate various customized kernels as execution proceeds greatly reduces the space requirements. When the kernel execution is carefully scheduled considering also the reconfiguration overheads, the obtained performance gain can offset such overheads. A policy and experiments will be presented of customizing and reconfiguring multiprocessor hardware for embedded benchmark kernels implemented on FPGAs. The results reveal substantial performance improvement and resource conservation.