Communication Driven Interconnect Synthesis
Chuck Monahan, Forrest D. Brewer · 1995
Chuck Monahan and Forrest Brewer1.0 IntroductionUntil recently, the emphasis in automated datapath construction was optimizationthrough reduction of resources due to area constraints. Lately, this constraint has relaxedsomewhat with the reduction of minimal feature sizes and the expansion of die sizes. Thisshift has led to a reevaluation of existing algorithms as designers construct higher perfor-mance, faster designs. In particular, the relative delays of data-path function units versusthat of the interconnection and bussing overhead has decreased enormously and is pre-dicted to do so for some time to come. While the trend in chip and MCM designs hasbegun to favor global point to point bussing, it is clear that these techniques do use up agreat deal of area and therefore increase the communication delay through fringing capac-itance and growth of physical interconnect distance. Linear data-path bussing offers afavorable topological density and ease of design, but current tools tend to minimize theinterconnect hardware without regard to the effects such minimization has on the perfor-mance of the design. These circumstances require more powerful tools to allow flexibledesign while modeling the performance and area costs accurately. In particular, for lineardata-path structures, we wish to accurately characterize the delays of the switching ele-ments, their sizes, the delays of the physical busses distributed RC delays, physical posi-tioning information of the components, and critical path delays for scheduled operationsincluding control unit and interconnection overhead.Achieving these ideals requires a new approach to datapath synthesis. First off, the sys-tem must be modeled in more exacting detail. Communication resources must beaccounted for in the design and these resources must comprise a larger family of compo-nents reflecting the trade-offs of high performance design. Specifically, components suchas bus drivers, receivers, switches and buffers must be modeled as well as conventionalmultiplexers. Furthermore, each assigned communication must impart positional informa-tion to the model since transmission delays are highly related to the distributed RC delayof the bus as well as the switching elements. Towards this aim, a pair of programs havebeen created: Timing Driven Communication Placement (TDCP) and Timing DrivenCommunication Interconnect (TDCI) systems [SeB91]. In these systems, the process ofdatapath synthesis has been broken down into two tasks. The first task, performed byTDCP, takes scheduled register transfer language commands in addition to a list ofresources and constructs the placement, function unit and register bindings for the datap-ath. While TDCP adopts a crude rating of the required interconnect as it judges designs, itdoes not create the actual interconnect. Instead it relies on a heuristic model of the trackdensity and communication times specific to the implementation technology.The second stage of the process is the focus of this report and is conducted by TDCI.TDCI assigns the communications proposed by TDCP into a realizable interconnectionstructure using a very general connection model to meet the design requirements imposedby TDCP. These constraints are described in terms of TDCI’s objective functions. The