Fault-Tolerant Nostrum NoC on FPGA for the ForSyDe/NoC System Generator Tool Suite
Salvator Gkalea · 2014
Moore’s law is the observation that over the years, the transistor density will increase, allowing billions of transistors to be integrated on a single chip. Over the last two decades, Moore’s law has enabled the implementation of complex systems on a single chip(SoCs). The challenge of the System-on-Chip(SoC) era was the demand of an efficient communication mechanism between the growing number of processing cores on the chip. The outcome established an new interconnection scheme (among others, like crossbars, rings, buses) based on the telecommunication networks and the Network- on-Chip(NoC) appeared on the scene.The NoC has been developed not only to support systems embedded into a single processor, but also to support a set of processors embedded on a single chip.Therefore, the Multi-Processors System on Chip(MPSoC) has arisen, which incorporate processing elements, memories and I/O with a fixed interconnection infrastructure in a complete integrated system. In such systems, the NoC constitutes the backbone of the communication architecture that targets future SoC composed by hundred of processing elements. Besides that, together with the deep sub-micron technology progress, some drawbacks have arisen. The communication efficiency and the reliability of the systems rely on the proper functionality of NoC for onchip data communication. A NoC must deal with the susceptibility of transistors to failure that indicates the demand for a fault tolerant communication infrastructure. A mechanism that can deal with the existence of different classes of faults(transient, intermittent and permanent [11]) which can occur in the communication network.In this thesis, different algorithms are investigated that implement fault tolerant techniques for permanent faults in the NoC. The outcome would be to deliver a faulttolerant mechanism for the NoC System Generator Tool [29] which is a research in Network-on-Chip carried out at the Royal Institute of Technology. It will be explicitly described the fault tolerant algorithm that is implemented in the switch in order to achieve packet rerouting around the faulty communication links.