High Level Analysis of Clock Regions in A C++ System Description
Luc Rynders, Patrick R. Schaumont, Serge Vernalde, Ivo Bolsens · 2000
Abstract Timing verication of digital syn chronous designs is a complex process that is tradi tionally carried out deep in the design cycle at the gate level A method embodied in a C based de sign system is presented that allows modeling and verication of clock regions at a much higher level By combining eventdriven clockcycle true and be havioral simulation we are able to perform static and dynamic timing analysis of the clock regions In addi tion a signicant increase in the design cycle speed is obtained Lets rst consider a small example\t that illustrates the targeted applications In a cable communication system there is a need for a