Scalable Logic Synthesis using a Simple Circuit Structure
Alan Mishchenko, Robert K. Brayton · 2006
This paper proposes an alternate approach to logic synthesis using rewriting and peephole optimization but from a modern perspective. We use a simple logic structure (AIGs) as the basis for all the algorithms, and rely on efficient techniques, such as precomputation, reconvergence analysis, cut enumeration, Boolean matching, exhaustive simulation of small logic cones, and local resource-aware decision procedures based on Boolean satisfiability. The result is a logic synthesis flow that is orders of magnitude faster than traditional ones and more scalable, being applicable to large industrial netlists with millions of gates.