Design and Implementation of a CMOS Chip for a Prolog
Stuart L. Graham, Vason P. Srini, Jerric V. Tam, Tam Minh Nguyen, Bruce K. Holmer · 1988
We have designed and fabricated a high performance VLSI chip for executing Prolog programs using a 1.4 micron CMOS technology with two layers of metal. This chip implements a tagged architecture with hardware support for five stacks. The 32-bit data path of the chip contains a fast ALU, 64 registers in four groups, five counters, and six non-master/slave registers. The control is microprogrammed and uses a 512 X 160 bit ROM with four pages for fast microbranching. The chip operates at a cycle time of 100 ns (worst case) and has a size of 10 mm X 9 mm. A semicustom design methodology employing Mentor and NCR tools has been used in design. The challenges involved in the design, verification, routing, and fabrication of the chip are described.