An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU
Fumio Arakawa, T. Yoshinaga, Tomoichi Hayashi, Y. Kiyoshige, T. Okada, M. Nishibori, T. Hiraoka, M. Ozawa, T. Kodama, T. Irita, Tatsuya Kamei, Makoto Ishikawa, Y. Nitta, O. Nishii, T. Hattori · 2004
An embedded-processor core implemented in a 130nm CMOS process runs at 400MHz and achieves 720MIPS with a power of 250mW and 2.8GFLOPS. The processor employs a dual-issue seven-stage pipeline architecture while maintaining 1.8MIPS/MHz instruction efficiency of the previous five-stage processor. The processor is suitable for digital consumer appliances.