A Low Complexity and A Low Latency Systolic Arrays for Multiplication in GF($2^m$) Using An Optimal Normal Basis of Type II
Soonhak Kwon, Yun-Ki Kwon, Chang‐Hoon Kim, Chun-Pyo Hong · 2008
Using the self duality of an optimal normal basis(ONB) of type II, we present a bit parallel and bit serial systolic arrays over GF() which has a low hardware complexity and a low latency. We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches(flip-flops). Comparing with other arrays of the same kinds, we find that our array has significantly reduced latency and hardware complexity.