Theory, design, and simulation of GASP: a block data flow architecture for gallium arsenide super computers
Douglas J. Fouts · 1991
The advantages and disadvantages of using high-speed gallium arsenide (GaAs) logic for implementing digital systems are reviewed. A set of design guidelines is presented for systems that will be constructed with high-speed technologies such as GaAs and silicon emitter coupled logic (ECL). A new class of computer and digital system architectures, know as functionally modular architectures, is defined and explained. Functionally modular architectures are ideal for implementation in GaAs because they adhere to the design guidelines. GASP, a new, functionally modular, block data flow computer architecture is then described. SPICE simulations indicate that if constructed with existing GaAs IC technology, parts of GASP could run at a clock speed of 1 GHz, with the rest of the architecture using a 500 MHz clock. The new architecture uses data flow techniques at a program block level, which allows efficient execution of parallel programs while maintaining reasonably good performance on sequential programs. A simulation study of the architecture's best case and worst case performance is presented. Simulations of GASP executing a highly parallel program indicate that an instruction execution rate of over 30,000 MIPS can be attained with a 65 processor system.