Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang J. Chen · 2021
Multisite testing significantly increases throughput by testing multiple chips simultaneously. When implemented on a large scale (massive multisite), the complex signal routing involved, interference, and coupling on the test hardware (amongst other issues) often affect test sites differently, introducing variations in site measurements. We hypothesize in this paper that each test site’s measurement can be modeled as a weak nonlinear function of the true chip measurement with systematic errors. We propose an algorithm to detect these systematic errors and calibrate them. This approach provides a practical black box technique to mitigate test hardware variations while investigating the fundamental root causes. The proposed method is verified with simulation and real test data.