A Development Support Tool for Fault-tolerant Routing Methods on Network-on-Chips
Yota Kurokawa, Daiki Kajimoto, Masaru Fukushi · 2021
Toward the realization of dependable high-end consumer electronics products, it is indispensable to design an efficient fault-tolerant packet routing method to enhance the communication performance of Network-on-Chip (NoC) based many core processors. The development of fault-tolerant routing methods is not an easy task because each path depending on the source and destination of each packet and the location of failures. If support tools exist for this purpose, we think that the development of methods will progress. NoC simulators such as noxim and booksim have been developed, however there are few tools to support the development of routing methods. In this paper, we develop a tool to assist in the development of fault-tolerant routing methods.