Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT
Heping Yang, Hui Chen, Yuxiang Fu, Li Li · 2021
The current multiplication and division IP imple- mentation are mainly achieved through LUT-based and iterative methods. This paper proposes a new hardware architecture, for fast calculating the multiplication and division of floating-point data. By mapping the multiplication and division operations to and , based on the mathematical characteristics of the two functions, Symmetric-Mapping LUT method can quickly calculate the floating-point multiplication and division, which has better low-latency characteristics and smaller area than that of the traditional method. The proposed multiplication and division architecture was synthesized under TSMC 40nm CMOS technology. The area is 14941.832µ at the frequency of 1GHz. On top of that, the proposed architecture reduces the latency to 3 cycles.