Leveraging Bloom Filters for Smart Search Within NUCA Caches
Robert Ricci · 2006
It is well-known that on-chip wire delays are emerg-ing as a major bottleneck in the design of highperformance microprocessor chips. As feature sizesare reduced, wire delays do not scale down at the same rate as logic delays [1, 5]. It has been projected that at35nm technologies, less than 1 % of the total chip area will be reachable in a single cycle [1]. Communication