Pipelined Shapiro sorting for image applications
Sowmya Kayala, Vasanth K. R · AIP conference proceedings · 2021
This paper introduces a novel VLSI architecture for Shapiro pipelined architecture. The proposed architecture is implemented on a fixed 3*3 window to sort nine elements of a window in ascending order. The proposed architecture is synthesized and simulated on Xilinx 7.1 compiler and modelsim PE student edition 10.4a and targeted on the device XCV600e-8fg676. The proposed architecture is compared with other sorting architectures and the corresponding outputs are compared. It was found that the proposed pipelining architecture uses only 19 comparators with a maximum frequency of 74.934 MHZ. Also, it was noted that the number of slices was reduced to 305 and the total power consumption to only 7mw. Hence this model exhibits high speed in operation with reduced power and area as compared to other architectures.