Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices
Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu · 2021
We introduce a scalable hardware architecture for large-scale invertible logic. Invertible logic has been recently presented that can realize bidirectional computing probabilis-tically based on Hamiltonians with a small number of non-zero elements. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, the proposed scalable invertible-logic hardware based on PTELL is designed on Xilinx KC705 FPGA board, which achieves two orders of magnitude faster than an 8-core CPU implementation.