A Low Power Binary CAM using 7T SRAM cell with increased substrate bias
Ganapavarapu Surekha, N Balaji, Y. Padma Sai · 2021 2nd International Conference on Smart Electronics and Communication (ICOSEC) · 2021
Leakage power reduction is an important metric to consider as technology progresses. A Binary CAM is introduced in this paper, which reduces leakage power caused by an increase in substrate bias in a transistor. This proposed design was tested in the virtuoso simulator using 45nm, 90nm, and 180nm tools. Investigation of the results show that the Binary CAM is reducing the dynamic power by 29.11%, 38.64%, 56.9% for matched condition and 34.78%, 41.51%, 75.48% for mis-matched condition in 45nm, 90nm and 180nm tools respectively. All these outcomes are compared with conventional Binary CAM and Binary CAM [25].