Flexible Parallel Processing in Memory: Architecture + Programming Model
Nael Abu‐Ghazaleh, Philip A. Wilsey, Jerry L. Potter, Robert A. Walker, Johnnie W. Baker · 1999
this paper we propose a PPIM that targets e- 1 cient exploitation of the internal bandwidth on a PIM, while providing a programming model that allows this bandwidth to be harnessed by a large class of algorithms. The proposed parallelism model is based on a dynamically partitionable distributed Multiple SIMD (MSIMD) [2, 14, 20]. Under this model, a small number of control units concurrently controls the PEs; each PE receives its control from exactly one of the control units. This model, like other model targeting lowlevel data-parallelism, can directly utilize data/stream parallelism to take advantage of the internal DRAM bandwidth [13,18]. In addition, the architecture also supports a limited degree of control-parallelism consistent with that present in most algorithms. Thus, the model balances the algorithmic needs with architecture capabilities. While the MSIMD model is not new, its ecient implementation in a PIM environment requires the introduction of several innovative techniques. For example, we present memory organizations that allow the raw DRAM bandwidth to be exploited even when PEs controlled by dierent controllers share the same memory bank