Multi-Prime RSA Verilog Implementation Using 4-Primes
T.D. Pathirage, H.P.D.K. Wijewardana, L.A.S. Lakshan, Hassaan Hydher, S.L.P. Yasakethu · 2021
In this paper, we present a new method to perform RivestShamirAdleman (RSA) key generation and decryption using FPGA. Multi-prime RSA uses more than two primes for computations. Here, we have used four primes for our hardware implementation. However, in this paper, we are not focusing on the random prime number generation. It can be externally computed and sent to the FPGA through peripheral component interconnect (PCI) port in the real scenario. We hard-coded the prime numbers and focused on the RSA key generation and decryption process. The importance of this implementation is that we use constant public e value 65537, which applies in OpenSSL with different n and d private key values for each RSA channel.