A Fault-tolerant Routing Method for 2D-torus Network-on-Chips Based on Bus Functions
Taiki Tomita, Yota Kurokawa, Masaru Fukushi · 2021
This paper deals with the issue of designing a fault-tolerant routing method for two-dimensional (2D) torus-connected Network-on-Chips (NoCs). 2D torus network contains several rings inside the network; therefore, it is not an easy task to design a fault-tolerant routing method that guarantees deadlock-freeness and 100% packet reachability. In this paper, we focus on the network on which packet routing is performed, and propose a method for realizing fault-tolerant routing with a well-known dimension order routing method. We extend the network architecture to make capable of utilizing faulty nodes as bus components. Performance evaluation shows that the proposed method improves throughput and latency by about 20.6% and 78.6 %, respectively, compared with an existing method. In addition, the amount of additional hardware is about 11 % for the whole circuit.