Hls Code Transformation Strategies And Directives Exploration For Fpga Accelerated Ecg Analysis
Vasileios Tsoutsouras, Konstantina Koliogeorgi, Sotirios Xydis, Dimitrios Soudris · Zenodo (CERN European Organization for Nuclear Research) · 2018
Electrocardiogram analysis has been established as a key factor for analysing and assessing the health status of a person. The ECG analysis flow is complex, relies on machine learning algorithms such as Support Vector Machines classifier and in an effort to be executed in real-time Hardware acceleration is required. In this paper we focus on utilizing High Level Synthesis capabilities to produce efficient SVM hardware accel- erators, targeting ECG analysis. Our case study is arrhythmia detection using MIT-BIH ECG signal medical database. We show that as a first step, the original code under acceleration can be re-structured in order to create instances which are efficiently transformed into a HW accelerator. As a second step, an exploration is performed on the transformed code in order to determine which HLS directives produce the best outcome in terms of various performance and resources utilization metrics. Our combined analysis shows that we can achieve results of up to 94% execution latency gain compared to the original SVM code and the designer is provided with the infrastructure necessary in order to decide the best trade-off between gains in latency versus increase in utilized FPGA HW resources.