Review on Recent Advances in VLSI Multiplier
Sulbha Bhongale, Yogesh Khandare, Santosh M. Bobade · Zenodo (CERN European Organization for Nuclear Research) · 2021
Low power very large-scale integration (VLSI) circuit is vital criteria for designing an energy efficient design for prime performance and the compact device design. Multiplier plays an important role for planning the energy economical processor that determine the potency of the processor. Multiplier has important role in DSP, DIP, microprocessor, and microcomputer application. Among all the arithmetic operation that exist, a processor consumes most of the time and hardware resources for carrying out multiplication when compared to other operations like addition and subtraction. In this review, Array multiplier, Booth multiplier, Modified booth multiplier, Wallace tree multiplier, and Modified booth allace tree multiplier have been reviewed considering several performance parameters, such as speed, area, power consume, circuit complexity. The fast multiplier is desired in any application. While comparing various multipliers, it has been observed that the selecting an appropriate multiplier for any application is always a tradeoff between speed, power and the area. Array multiplier has the largest delay and low power consumption and have large area, while booth encoded allace tree multiplier has least delay and it also have large area. In above multipliers, one of the limitations is no of partial products. The booth algorithm for multiplication overcomes the limitation and hence, the performance is improved. In this review, the booth algorithm and its variant which outperform the several multipliers will be discussed. The detail comparison of multipliers and their performance matrix in term of delay, area and power consumption will be provided, so that the most appropriate multiplier can be chosen for application.