Scalable Digital Synchronizer for Enabling Hardware-Level BLE Mesh Networks under 1 mW
Ivan Bukreyev, Ken Ho, Alyssa Apsel · 2021
We present a hardware accelerator, fabricated in 180 nm CMOS, for baseband timing of BLE mesh networks. The timing circuitry augments the BLE physical layer with a new command that enables scalable synchronization and aggressive duty-cycling of mesh nodes for low-power P2P communication. The custom ASIC contains a digital correlator which enables low-latency detection of a BPSK synchronization packet, or syncword. The detected syncword advances the phase of a nonlinear pulse-coupled oscillator, which drives the network to a synchronized state. The accelerator interfaces with the AD9364 software-defined radio via a ZedBoard to make a fully functional node. Duty-cycled multi-hop communication is demonstrated with total power consumption per radio node of less than 1 mW while communicating 64-bit 10 MSPS packets.