Design of High Speed and Low Area Masked AES Using Complexity Reduced Mix-Column Architecture
J. Balamurugan · 2014
In this paper, presents optimized mix column architecture to get less area and delay than the existing mix column. Because the proposed mix column architecture is reduced using Xtime unit. In the existing architecture, we are used complex mix-column in masked AES architecture. It consists of 8 multipliers and 11 adders.