Area Efficient Hexadecimal Divider Circuit Implementation Based on USP-Awadhoot Division Algorithm
Udayan Sunil Patankar, Ants Koel, Sunil Patankar, Miguel E. Flores · 2021
Arithmetic operations are crucial in the current age of technology and development. Electronic implementation of mathematical operations is a very important and critical part of a digital system. Even though the number of transistors on a chip, increases beyond Moore's law prediction, it is quite complicated to implement arithmetical operations; a sophisticated algorithm is essential to successful implementation. Different dividers have been developed based on various algorithms to provide better results for division implementation in digital hardware. Generally, the major aspects considered are quotient convergence rate, hardware primitives, area overheads, and mathematical formulation. Many algorithms were implemented to achieve dividers, which provide a solution with or without any error percentage. Although many error-resilient applications exist, such dividers fail to work satisfactorily in terms of power consumption and overall circuit performance. In some cases, estimation and approximation-based dividers are used to provide faster usage with a considerable error, but digit recurrence algorithms are used in most commercial applications, which requires more area. Thus, we developed a new, three-stage zero error digit recurrence USP-Awadhoot division algorithm. The present article illustrates the design and implementation statistics of an area-efficient divider circuit based on a novel USP-Awadhoot division algorithm and the effective use of a hexadecimal number system to achieve ease in quotient conversion logic.