Assertion Based Design of Timed Finite State Machine
Alexander Shkil, Anatolii Mіroshnyk, Georgiy Kulak, Кирило Юрійович Пшеничний · 2021
This work is dedicated to assertion-based verification of real time logic control systems that are specified by a state diagram with state looping and implemented by hardware description language. The proposed method is based on the assertion apparatus that is used to describe the temporal nature of the timed FSM properties.